An analog comparator receives first and second analog signals and produces an output signal according to respective voltage values of the first and second analog signal. The output signal has a first value, such as ‘0’, when the voltage value of the first analog signal is less than the voltage value of the second analog signal plus an offset voltage. The output signal has a second value, such as ‘1’, when the voltage value of the first analog signal is greater than the voltage value of the second analog signal plus the offset voltage.
The analog comparator may perform the comparison of the values of the first and second analog signals at a time determined according to a clock signal. The analog comparator may latch the result of the comparison, and therefore function as a latch.
The comparator may be used, among other applications, in a Serializer/Deserializer (SERDES) receiver circuit or an Analog to Digital Converter (ADC) circuit. The ADC circuit may include any of a flash ADC, a sigma-delta ADC, a successive approximation ADC, an interleaved ADC, a single-slope or multi-slope ADC, and the like.